Here we provide a list of Free EDA/HDL tools that we have written, and links to other sites that also provide free EDA tools.
Tools Developed by ASICS.ws
All Free Tools (developed by ASICS.ws) are distributed under a modified BSD
TopGen is a perl script that takes one or more Verilog Modules and connects them together in a newly generated top level module. It can take a top level module prototype as an optional input as well. Further it supports aliases where signals with different names in the modules are connected together on the top level using a common signal name. Automatic width specification is also performed. The resulting top level will most likely still require manual editing, but 99% of the tedious copy, paste and typing work is eliminated.
Download TopGen v1.1 (topgen.gz 3kb)
Links to Free EDA tools provided by others
If you know of an excellent EDA tool that you think we should list here, please
drop us a line
! - Thanks !
Icarus Verilog Simulator
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as
a compiler, compiling source code written in Verilog (IEEE-1364) into some
target format. For batch simulation, the compiler can generate an intermediate
form called vvp assembly. This intermediate form is executed by the 'vvp'
command. For synthesis, the compiler generates netlists in the desired format.
The compiler proper is intended to parse and elaborate design descriptions
written to the IEEE standard IEEE Std 1364-2001.
GPL Cver is a Verilog HDL simulator that is released under the GNU General
Public License. GPL Cver is a full 1995 P1364 Verilog standard HDL
simulator. It also implements some of the 2001 P1364 standard features
including all three PLI interfaces (tf_, acc_ and vpi_) as defined in the
2001 Language Reference Manual (LRM).
Cver runs on Linux, Sparc, and OSX.
The CRC tool allows you to specify a custom polynomial or to chose one from
a list of popular standard polynomials, and generates a Verilog or VHDL module
to compute the CRC based on the specified polynomial. It also allows you to
specify the data bus width.
Arithmetic Module Generator
the arithmetic module generator will generate add, subtract, multiply, squarer
and wallace tree modules. Many, many, option such as data bus width and pipeline
stages. It will generate either Verilog or VHDL code.
GEDA is a collection of GPL'ed EDA tools. This collection consists of many great
tools,such as schematic capture, CPICE, wave form viewers. However, many of the
tools are still under development.
OpenCollector is not really a tool, but one of the best resources for free tools
and IP cores in the industry. In addition to providing a huge database of free
tools, and utilities, it also provides a News section.
VeriPool - A collection Public Domain Verilog Resources
This collection includes many useful tools, including
Verilator (a Verilog to C and System C translator) and Dinotrace
(A free waveform viewer for Linux and Windows).