Free ip cores 

USB 1.1 Physical Interface core. This core provides all functions essential to interface to the USB 1.1 bus. This includes serial/parallel conversion, bit stuffing and unstuffing, NRZI encoding and decoding and a DPLL. It comes with a industry standard UTMI interface for easy portability

Technology	Area	Speed
Xilinx Spartan 2 xc2s50-6	111 LUTs (30%)	> 50 MHz

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page NOTE: This implementation example includes the usb 1.1 PHY IP Core and two 64 byte control endpoint FIFOs. Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

USB 1.1 compliant device core. Internally it provides a very easy to use FIFO interface, externally it features a UTMI interface to hock up a USB 1.1 compatible PHY. This core performs all USB required enumeration in hardware. There is no need for an additional microcontroler. It stores device and configuration descriptors in a ROM. Sample Implementation Results

Technology	Area	Speed
Xilinx Spartan 2e xc2s100e-6	885 LUTs (36%), 515 Reg. (21%)	80 MHz

NOTE: This implementation example includes the usb 1.1 PHY IP Core and two 64 byte control endpoint FIFOs.

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language.

To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

A USB 2.0 compliant device controller. Provides transfer speeds of over 480Mbps. Easy integration in to an existing system utilizing WISHBONE bus interface. Provides UTMI interface for easy PHY integration (internally or externally). Sample Implementation Results

Technology	Area	Speed
Xilinx Spartan 2 xc2s50-6	111 LUTs (30%)	> 60 MHz

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

Very simple serial interface core. Provides hardware handshake (RTS & CTS), and a fixed 1 start, 1 stop bit data format. Internal interface is through 4 byte deep FIFOs. Sample Implementation Results

Technology	Area	Speed
Xilinx Spartan 2e xc2s50e-6	83 LUTs (5%)	100 MHz

NOTE: This implementation did NOT include a baud rate generator. Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

This core provides a slave interface to a single slot PCM stream. It captures and transmits 16 bit samples a the SYNC interval. Allows to interface to such popular devices like TI DSPs (via McBSP bus) in PCM mode
Sample Implementation Results

Technology	Area	Speed
Xilinx Spartan 2e xc2s50e-6	38 LUTs (2%)	125 MHz

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

This core provides an easy interface to AC97 Audio Codecs. It supports variable and fixed sample rates, 16-20 bits sample sizes, and full 6 channel audio. It is WISHBONE compliant and can directly interface to an external DMA engine.
Sample Implementation Results

Technology	Area	Speed
Xilinx Spartan 2e xc2s100e-6	1704 LUTs (71%)	100 MHz

NOTE: This sample implementation implements the full AC97 controller with all 6 channels. Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

Implements a master interface to the famous I2C bus from Philips (compatible with SMBus). Supports single and multi master operations, clock stretching, polled and interrupt driven operations. Can perform 7 or 10 bit addressing. Timing is user programmable.
Sample Implementation Results

Technology	Area	Speed
Actel A54SX16ATQ100-std	329 Modules	53 MHz
Altera FLEX EPF10K50EFC256-1	288 lcells	110 MHz
Altera ACEX EPF1K50FC256-1	288 lcells	100 MHz
Xilinx Spartan-II 2s100fg256-6	113 CLB	80 MHz
Xilinx Virtex-E v100efg256-8	113 CLB	127 MHz
Xilinx Virtex-II 2V250fg256-5	111 CLB	90 MHz

Currently this IP Core is available in Verilog and VHDL only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

This Core provides direct interface to ATA compliant devices, such as Hard Drives, CDROMs, PC-Cards, Compact Flash, etc. Three versions of this core are available depending on your needs. Choose from a very simple and small single device version to a full featured version with DMA support.
Sample Implementation Results for OCIDEC-1 This version supports PIO transfer only. It provides a single timing register for all accesses to the connected devices.

Technology	Area	Speed
Altera ACEX EPF1k100FC484-1	262 lcells	111 MHz

Sample Implementation Results for OCIDEC-2 This version supports PIO transfer only. It provides common timing register for all compatible accesses to the connected devices. And separate timing register per device for fast DataPort accesses.

Technology	Area	Speed
Altera ACEX EPF1k100FC484-1	439 lcells	111 MHz

Sample Implementation Results for OCIDEC-3 This version supports: - PIO, Single-Word DMA and Multi-Word DMA transfer support. - Common timing register for all PIO compatible accesses to the connected devices. - Separate timing registers per device for fast PIO DataPort accesses. - Separate timing registers per device for DMA transfers. - PIO write access ping-pong. - WISHBONE Retry cycles for PIO accesses while controller busy.

Technology	Area	Speed
Altera ACEX EPF1k100FC484-1	916 lcells	84 MHz

Currently this IP Core is available in Verilog and VHDL only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

This is a Motorola DragonBall/68K to Wishbone bridge. The core translates the 16bit DragonBall/68K bus into a full featured 16bit Wishbone master bus. Features 16bit Motorola DragonBall/68K Interface 16bit full featured RevB.3 Wishbone Classic Master interface Programmable address-bus size Static synchronous design Fully synthesisable
Sample Implementation Results

Technology	Area	Speed
XILINX Spartan 2	6 LUT
Altera ACEX	32 LCELLs

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

Enhanced version of the Serial Peripheral Interface available on Motorola's MC68HC11 family of CPUs. Enhancements include a wider supported operating frequency range, 4 deep read and write FIFOs, and programmable transfer count dependent interrupt generation. As with the SPI found in MC68HC11 processors the core features programmable clock phase (CPHA) and clock polarity (CPOL). The core features an 8bit wishbone interface. Wider wishbone interfaces are easily supported by using multiple instances. Very simple, very small.
Features 4 entries deep read FIFO 4 entries deep write FIFO Interrupt generation after 1, 2, 3, or 4 transfered bytes Static synchronous design Fully synthesizable
Sample Implementation Results

Technology	Area	Speed
XILINX Spartan 2	130 LUTs
Altera ACEX	230 LCELLs

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

A small micro controller IP core compatible with the popular Microchip PIC16C57. This implementation executes one instruction per cycle. This version has 3x 8 bit I/O ports and up to 2K instruction memory. Sample Implementation Results

Technology	Area	Speed
Xilinx Spartan IIe-50	30%	80 MHz (== 320 MHz PIC)

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

The goal of this project is to build a TI 54x DSP compatible IP core. It will utilize a 5 stage pipeline and have 4 external WISHBONE interfaces for maximum performance.
Sample Implementation Results

Technology	Area	Speed

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

Traditional DES engine. Two versions are provided, an area optimized and a performance optimized. The Area Optimized (CBC Mode) version needs 16 cycles to complete a full encryption/decryption cycle. The Performance Optimized (EBC Mode) version is a pipelined implementation that has a 16 cycle pipeline (plus 1 input and 1 output register). It can perform a complete encryption/decryption every cycle. Sample Implementation Results Area Optimized Version

Technology	Area	Speed
Xilinx Spartan II-50	87%	100 MHz (400 Mbit/sec)
0.18u UMC	3K gates	155 MHz (620 Mbit/sec)
Altera APEX 20KE-1	1106 lcells	27 MHz (108 Mbit/sec)
Altera FLEX 10K50E-1	1283 lcells	43 MHz (172 Mbit/sec)

Sample Implementation Results Performance Optimized Version

Technology	Area	Speed
Xilinx Spartan II-200	94%	140 MHz (8.9 Gbit/sec)
0.18u UMC	28K gates	290 MHz (18.6 Gbit/sec)
Altera APEX 20KE-1	6688 lcells	53 MHz (3.4 Gbit/sec)
Altera FLEX 10K50E-1	6485 lcells	76 MHz (4.8 Gbit/sec)

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

Triple DES engine. Two versions are provided, an area optimized and a performance optimized. The Area Optimized (CBC Mode) version needs 48 cycles to complete a full encryption/decryption cycle. The Performance Optimized (EBC Mode) version is a pipelined implementation that has a 48 cycle pipeline (plus 1 input and 1 output register). It can perform a complete encryption/decryption every cycle.
Sample Implementation Results Area Optimized Version

Technology	Area	Speed
Spartan IIe 100-6	1450 LUTs (60%)	88 MHz (117 Mbit/sec)
0.18u UMC	5.5K Gates	160 MHz (213 Mbit/sec)

Sample Implementation Results Performance Optimized Version

Technology	Area	Speed
Virtex-II-1500-6	79%	166 MHz (10.6 Gbit/sec)
0.18u UMC	55K Gates	300 MHz (19.2 Gbit/sec)

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

Simple AES Rijndael Crypto IP Core. This implementation was designed with the goal in mind that it should fit in to a low cost FPGA (such as a Spartan IIe from Xilinx) and provide reasonable performance. The Free version comes with a 128 key expansion module only. Other Implementations of the AES Rijndael IP core with different key sizes (192 & 256 bit) and performance attributes (like a fully pipelined ultra-high-speed version) are commercially available from ASICS.ws. Pleaseemail us for more information.
Sample Implementation Results for Cipher Block

Technology	Area	Speed
Xilinx Spartan IIe XS2V200-6	3497 LUTs (74%), 1026 Regs. (21%)	101 MHz (1.08 Gbit/sec)
UMC 0.18u Std. Cell	38K Gates	265 MHz (2.82 Gbit/sec)

Sample Implementation Results for Inverse Cipher Block

Technology	Area	Speed
Xilinx Spartan IIe XS2V200-6	3393 LUTs (72%), 883 Regs. (18%)	85 MHz (906 Mbit/sec)
UMC 0.18u Std. Cell	50K Gates	235 MHz (2.5 Gbit/sec)

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

This is a IEEE754 compliant single precision floating point unit. It has a 4 stage pipeline and can execute an operation every clock cycle. It includes Add, Subtract, Multiply and Divide operations, supports rounding to Nearest Even, Round to Zero, Round to +INF and Round to -INF. Sample Implementation Results

Technology	Area	Speed

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

The CORDIC algorithm is an iterative algorithm to evaluate many mathematical functions, such as trigonometrically functions, hyperbolic functions and planar rotations.
Sample Implementation Results

Technology	Area	Speed
Xilinx Spartan-II xc2s50-6	869 LUTs(56%), 799 reg. (52%)	102 MHz

Currently this IP Core is available in VHDL only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

This is a collection of several dividers. All dividers are fully synthesizabel and parameterized. All dividers are pipelined and can perform an operation every clock cycle.
Sample Implementation Results

Technology	Area	Speed
Xilinx Spartan 2e xc2s100e-6	1132 LUTs (47%) and 1736 reg. (72%)	82 MHz

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

This is a fully pipelined, parallel implementation of an 8x8 DCT Unit. It can generate a DCT result every clock cycle, or an entire 8x8 DCT transform in 64 clock cycles. This is an equivalent of 4096 MAC operations per clock cycle. The amount of bits per coefficient is parameterized. The output of the DCT unit is already in the zig-zag format described in the JPEG, MPEG, and other standards.
Sample Implementation Results

Technology	Area	Speed
Xilinx Virtex-II xc2v3000-6	7533 LUTs (26%), 4401 Reg. (15%), 64 MULT18x18, 46Kbits (ROM)	110 MHz (7 GMAC/sec)

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

This is a Quantization & Rounding Unit as described in the JPEG, MPEG, and other specs. It is fully pipelined and can generate a result every clock cycle.
Sample Implementation Results

Technology	Area	Speed
Xilinx Virtex-II xc2v40-6	433 LUTs (84%), 449 Reg. (87%)	120 MHz

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

This is an Huffman based entropy encoder as described in the JPEG, MPEG and other specs. It transforms an input stream into a Huffman encoded output stream. Included in the design are JPEG's default Huffman tables for DC-luminance, DC-chrominance, AC-luminance, and AC-chrominance.
Sample Implementation Results

Technology	Area	Speed
Xilinx Virtex-II xc2v80-6	898 LUTs (87%)	110 MHz

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

This is an Huffman based entropy decoder as described in the JPEG, MPEG and other specs. It transforms a Huffman encoded input stream into a decoded output stream. Included in the design are JPEG's default Huffman tables for DC-luminance, DC-chrominance, AC-luminance, and AC-chrominance.
Sample Implementation Results

Technology	Area	Speed
Xilinx Virtex-II xc2v80-6	568 LUTs (55%)	81 MHz

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

Generic FIFOs that are shared between various projects. Fully parametarized, multi purpose implementations. Sample Implementation Results

Technology	Area	Speed

Currently these IP Cores are available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Cores and/or to download the full sources and documentation please visit the Project Page X

This DMA engine has two WISHBONE interfaces and can perform DMA transfers on either one of the two interfaces or act as a passive bridge. It features up to 31 channels, and up to 8 priority levels. Different buffer molds may be selected: Linear Access, Circular Buffers, and FIFO Buffers. It also provides Linked List Descriptors support in hardware. Further it supports hardware handshake and interrupts.
Sample Implementation Results

Technology	Area	Speed
Xilinx Spartan 2e xc2s100e-6	1730 LUTs (72%)	65 MHz

NOTE: This implementation is for a 4 channel version.
Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

This core provides an easy way to integrate numerous cores to create a SoC. It acts as a interconnect matrix and arbiter between up to 8 masters and 16 slaves. It provides up to 4 priority levels in it's arbiters and is fully configurable. Sample Implementation Results

Technology	Area	Speed

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language.
To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

Simple General Purpose IO port. It supports up to 8 GPIO pins. Each pin is individually programmable as either input or output. The core features an 8bit wishbone interface. Wider wishbone interfaces are easily supported by using multiple instances (e.g. 4 simple GPIO cores provide a 32bit wishbone interface). Very simple, very small.
Features

Up to 8 GPIO pins per core

Each GPIO pin individually programmable as either input or output

Static synchronous design

Fully synthesisable

Sample Implementation Results

Technology	Area	Speed
XILINX Spartan 2	11 LUTs
Altera ACEX	43 LCELLs

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

Simple programmable interrupt controller. It supports up to 8 interrupt sources. Polarity and sensitivity (either edge or level) is programmable per interrupt source. The core features an 8bit wishbone interface. Wider wishbone interfaces are easily supported by using multiple instances. Very simple, very small.
Features

Up to 8 interrupt sources

Sensitivity (edge/level) programmable per interrupt source

Polarity programmable per source

Static synchronous design

Fully synthesisable

Sample Implementation Results

Technology	Area	Speed
XILINX Spartan 2	48 LUTs
Altera ACEX	83 LCELLs

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

WISHBONE to OPB Bus Interface wrapper and OPB to WISHBONE Bus Interface wrapper provide an straight forward way to access peripherals that where written for WISHBONE on OPB bus and peripherals that have been written for OPB on a WISHBONE bus. Very simple, very small. Address space is direct mapped, allowing transparent access. Sample Implementation Results

Technology	Core	Area
XILINX FPGA (any)	OPB to WISHBONE	26 Slices, 74 Flip Flops, 45 LUTs
XILINX FPGA (any)	WISHBONE to OPB	44 Slices, 2 Flip Flops, 77 LUTs

Currently this IP Core is available as a pluggin for Xilinx EDK (netlist) only. Please email us if you need to have an IP Core translated to a different language. You can download this IP Core X

The memory Controller supports SDRAM, SSRAM, FLASH, ROM and other asynchronous and synchronous devices. It comes with 8 chip selects, and is fully programmable. Full support of burst operations as well as other special features such as leaving banks and rows open for increased performance. Dynamic bus sizing allows booting from 8 or 16 bit devices (such as flash). Sample Implementation Results

Technology	Area	Speed

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

This core provides an advanced interface to ZBT SSRAMs.
Sample Implementation Results

Technology	Area	Speed

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

Advanced interface for CRT and LCD monitors. Video timing is fully user programmable. Hardware support for 32, 24, and 16 bit color modes, as well as 8 bit gray scale and 8 bit pseudo color modes. Bank switching, triple display and two hardware cursor support also included. Sample Implementation Results

Technology	Area	Speed
Altera FLEX EPF10K50E-1	1112 lcells, 16080 mem_bits	82 MHz WISHBONE, 100 MHz pixel clock
Altera ACEX EPF1K50-1	1113 lcells, 16080 mem_bits	85 MHz WISHBONE, 107 MHz pixel clock
Altera APEX EPF20K60E-1	1142 lcells, 16080 mem_bits	47 MHz WISHBONE, 119 MHz pixel clock

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X

The Video Compression System project will include a variety of IP Cores to enable the end user to build various compression systems, such as MPEG-1, MPEG-2 and MPEG-4. As well as to provide support for H.310, H.320 etc. It will also include JPEG and Motion JPEG codecs.
Sample Implementation Results

Technology	Area	Speed

Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X