Free & Open IP Cores

Real RTL. Real test benches. Free.

We were the first company to provide free IP cores — full source, documentation and test benches under a modified BSD license, so you can use them in commercial products. Full technical support is available for most cores featured on OpenCores.

Networking, Communications & Connectivity

10 CORES

Core	Description	FPGA	ASIC	WISHBONE	HDL
USB 1.1 PHY	All functions essential to interface to the USB 1.1 bus (USB/UTMI). 111 LUTs, >50 MHz on Spartan-2.	●	●	—	Verilog
USB 1.1 Device	Very easy-to-use FIFO interface; UTMI hookup for a USB 1.1 compatible PHY. 885 LUTs, 80 MHz.	●	●	—	Verilog
USB 2.0 Device	USB 2.0 compliant device controller with transfer speeds over 480 Mbps via UTMI.	●	●	●	Verilog
Asynchronous Serial IO	Simple RS-232 serial core with RTS/CTS hardware handshake. 83 LUTs, 100 MHz.	●	●	—	Verilog
Single-Slot PCM Controller	Slave interface to a single-slot PCM stream; captures and transmits 16-bit samples. 38 LUTs.	●	●	—	Verilog
AC97 Controller	Easy interface to AC97 audio codecs: variable/fixed sample rates, 16–20-bit samples, full 6-channel audio.	●	●	●	Verilog
I2C Master Controller	Master interface to the Philips I2C bus; implementations across Actel, Altera and Xilinx.	●	●	●	Verilog + VHDL
ATA/ATAPI Host Controller	Direct interface to ATA devices — hard drives, CD-ROMs, PC-Cards, Compact Flash. Three versions (OCIDEC-1/2/3).	●	●	●	Verilog + VHDL
DragonBall/68K–Wishbone Bridge	16-bit Motorola DragonBall/68K interface to a full-featured Wishbone Classic master.	●	●	●	Verilog
Enhanced MC68HC11 SPI	Motorola MC68HC11-style SPI port with 4-entry read and write FIFOs.	●	●	●	Verilog

CPU, DSP & Microcontrollers

2 CORES

Core	Description	FPGA	ASIC	WISHBONE	HDL
Mini-RISC MCU (PIC clone)	Small microcontroller core compatible with the popular Microchip PIC16C57; 3 × 8-bit I/O ports. 80 MHz.	●	●	—	Verilog
Open 54x DSP Clone	TI 54x DSP-compatible IP core project built around a 5-stage pipeline.	●	●	—	Verilog

Encryption / Decryption

3 CORES

Core	Description	FPGA	ASIC	WISHBONE	HDL
DES	Traditional DES engine in two versions: area-optimized (16 cycles per operation) and a pipelined version that completes an encryption/decryption every cycle.	●	●	●	Verilog
Triple DES	3DES in area-optimized (48 cycles) and pipelined performance versions.	●	●	●	Verilog
AES (Rijndael)	Compact AES core designed to fit a low-cost FPGA. Free version includes a 128-bit key-expansion module.	●	●	●	Verilog

Math & Arithmetic

7 CORES

Core	Description	FPGA	ASIC	WISHBONE	HDL
Single-Precision FPU	IEEE-754 compliant floating-point unit with a 4-stage pipeline: add, subtract, multiply and divide.	●	●	●	Verilog
CORDIC Core	Iterative CORDIC algorithm for evaluating many mathematical functions. 869 LUTs, 102 MHz.	●	●	●	VHDL
Hardware Dividers	Collection of fully synthesizable, parameterized, pipelined dividers — one operation per clock cycle.	●	●	—	Verilog
8×8 DCT, fully pipelined	Parallel 8×8 DCT producing a result every clock — 4096 MAC operations per cycle (7 GMAC/s on Virtex-II).	●	●	—	Verilog
QNR Quantization	Quantization & rounding unit as described in the JPEG/MPEG specs; fully pipelined. 433 LUTs, 120 MHz.	●	●	—	Verilog
Huffman Encoder	Huffman-based entropy encoder per the JPEG/MPEG specs, with JPEG's default tables included.	●	●	—	Verilog
Huffman Decoder	Matching entropy decoder, also including JPEG's default Huffman tables. 568 LUTs, 81 MHz.	●	●	—	Verilog

Misc. Building Blocks

6 CORES

Core	Description	FPGA	ASIC	WISHBONE	HDL
Generic FIFOs	Fully parameterized, multi-purpose FIFO implementations shared across our projects.	●	●	●	Verilog
DMA / Bridge	Dual-Wishbone DMA engine — up to 31 channels and 8 priority levels — that can also act as a passive bridge.	●	●	●	Verilog
Wishbone Interconnect Matrix	Easy SoC integration: up to 8 masters and 16 slaves with up to 4 priority levels.	●	●	●	Verilog
Simple GPIO	Up to 8 GPIO pins, each individually programmable as input or output. 11 LUTs.	●	●	●	Verilog
Simple Interrupt Controller	Up to 8 interrupt sources with edge/level sensitivity programmable per source. 48 LUTs.	●	●	●	Verilog
Wishbone ⇄ OPB Wrappers	Direct-mapped, transparent access between Wishbone and OPB peripherals. Xilinx EDK plugin (netlist).	●	●	●	Netlist

Memory Controllers & Interfaces

2 CORES

Core	Description	FPGA	ASIC	WISHBONE	HDL
Advanced Memory Controller	Supports SDRAM, SSRAM, FLASH, ROM and other sync/async devices; 8 chip selects, fully programmable.	●	●	●	Verilog
SSRAM Interface	Advanced interface to ZBT SSRAMs.	●	●	●	Verilog

Video Controllers & Interfaces

2 CORES

Core	Description	FPGA	ASIC	WISHBONE	HDL
VGA/LCD Controller	CRT and LCD interface with fully programmable video timing; 32/24/16-bit color plus 8-bit grayscale and pseudo-color modes.	●	●	●	Verilog
Video Compression System	A family of cores for building MPEG-1/2/4, JPEG and Motion-JPEG compression systems.	●	●	—	Verilog

License

All free IP cores are distributed under a modified BSD license — free to use in commercial and non-commercial products. Redistributions must retain the copyright notice and disclaimer; the software is provided “as is” without warranty.

Downloads & support

All cores link to their OpenCores project pages for full documentation and downloads. We provide full technical support for most IP cores featured on the OpenCores web site — and commercial-grade versions of many of them.

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