Commercial IP Cores
Silicon-proven IP, ready to drop in.
Every core ships with documentation, a full test bench and synthesis scripts. Most have been written so they can be easily customized to meet your exact needs — and we can adapt any of them for you.
Storage & Disk Interfaces
6 CORESSAS Recorder IP Core
High-speed data recording supporting SAS 1.5, 3.0, 6.0 and 12.0 Gbps across up to 4 ports, with hardware-managed command sequencing and AXI streaming interfaces.
SAS Initiator IP Core
Multi-port SAS/SATA initiator with aggregate speeds up to 48 Gbps, frame assembly, power management and multi-channel DMA.
SATA I/II/III Host Controller
531 MB/s read and 505 MB/s write throughput; 66K/67K IOPS. NCQ, port multiplier support — SATA v3.0 compliance certified.
SATA I/II/III Device Controller
Device-side controller supporting 10/20/40-bit PHY interfaces, optional native-mode programming and comprehensive register implementations.
SD/SDIO/MMC Host IP
Compliant with the SD Host Controller specification. 1-bit, 4-bit and SPI modes, read cache and interrupt-on-completion.
SD/SDIO/MMC Target IP
Physical link interface for SD, SDIO and MMC devices with optional DMA and up to 4 KB of data buffering.
Security, Hashing & Compression
6 CORESAES Crypt IP Core
Up to 8 independent crypt engines delivering more than 2.4 GB/s. 128/192/256-bit keys, ECB, CBC and XTS modes, BitLocker acceleration.
Enhanced AES (Rijndael) IP Core
FIPS-197 compliant, with pipelined versions reaching 34 Gbit/s in 0.18µ and 14- or 24-cycle latency options.
HASH IP Core
MD5, SHA-1 and SHA-256 with scatter/gather DMA and independent clocks for each hash engine.
Keccak / SHA-3 / SHAKE IP Core
Modern sponge-construction hashing supporting the SHA-3 family and SHAKE extendable-output functions. Released January 2026.
HMAC IP Core
Hardware keyed-hash message authentication, pairing with our HASH and SHA-3 engines. Released January 2026.
ZLIB IP Core
Compression and decompression with fixed Huffman encoding and an LZ77 subset; configurable 32/64/128-bit data paths.
Post-Quantum Cryptography
4 CORESML-KEM IP Core (FIPS 203)
Module-lattice key-encapsulation accelerator: KeyGen, Encaps and Decaps with runtime selection of ML-KEM-512/768/1024. AXI4-Stream data and AXI4-Lite control, optional two-share masked datapaths and explicit zeroization — verified byte-exact against official NIST ACVP vectors. Around 2,900 encapsulations/s at 100 MHz on Kintex UltraScale.
ML-DSA IP Core (FIPS 204)
Module-lattice digital signature accelerator: key generation, deterministic or randomized signing, and verification with runtime selection of ML-DSA-44/65/87. Shared Keccak and NTT datapaths, 8–256-bit AXI4-Stream interfaces and explicit zeroization — verified against NIST ACVP vectors for all three parameter sets. Routed at 95 MHz on Kintex UltraScale+.
SLH-DSA IP Core (FIPS 205)
Stateless hash-based digital signatures covering all 12 standardized SHA2 and SHAKE parameter sets: key generation, deterministic or hedged signing, and verification. Scalable worker lanes and compile-time pruning span compact control-plane builds to high-throughput accelerators; verified with 1,248 official NIST ACVP tests.
FN-DSA / Falcon IP Core
Complete Falcon v1.2 raw signature service: Falcon-512 and Falcon-1024 key generation, randomized signing and verification built on SHAKE256, NTT and FFT/LDL engines, with 8–256-bit AXI streaming and explicit zeroization. Over 5,200 verifies/s on Artix-7 at 111 MHz. Qualified to the Falcon v1.2 profile (final FIPS 206 not claimed).
Error Correction & Coding
5 CORESLDPC & PHY FEC IP Core
QC- and SC-LDPC encoding with layered normalized min-sum decoding, plus complete 5G NR, Wi-Fi 802.11/802.11ad, DVB-S2 and CCSDS coding chains — rate matching, CRC, shortening, puncturing and BCH included. Independent 8–256-bit AXI4-Stream ingress and egress; six functional-coverage suites close at an enforced 100%.
BCH Encoder / Decoder IP Core
Systematic BCH encoding and multi-bit error-correcting decoding in one configurable core: codeword length, data length and correction capability (n, k, t) are all parameterizable, with configurable parallel bus widths and AXI4-Stream interfaces. Syndrome, Berlekamp-Massey and Chien-search decoding with uncorrectable-error reporting — built for NAND flash controllers, SSD/eMMC/UFS storage and communication systems.
GPON FEC 2.5 Gbps
Reed-Solomon forward error correction fully compliant with the 2.5 Gbps GPON standard; corrects up to 8 byte errors per codeword.
Reed-Solomon Decoder
Fully configurable decoder with dynamic code rates, programmable codeword lengths and error-correction parameters.
Reed-Solomon Encoder
High-performance encoder with 2-cycle latency and dynamic code-rate variation.
Wireless & Baseband
1 COREOFDM Transceiver IP Core
Complete TX/RX baseband: 64- to 2048-point FFT/IFFT, runtime-selectable BPSK to 64-QAM, configurable cyclic prefix, IEEE 802.11a/g-style preamble and carrier profiles, CFO estimation, zero-forcing or MMSE equalization, and hard decisions plus per-bit soft LLR output. Full- or resource-shared half-duplex operation with digital loopback; 250 MHz pre-layout ASIC closure and routed Artix-7 reference at ~200 MHz.
Connectivity & Peripherals
4 CORESUSB 3.0 Device IP Core
SuperSpeed 5 Gbit/s device controller with integrated DMA and up to 16 configurable endpoints.
USB 2.0 On-The-Go IP Core
Dual-role host/device capability at low, full and high speed across 16 endpoints. Compliance certified.
USB 2.0 Device IP Core
High-performance device controller: 16 endpoints supporting bulk, interrupt and isochronous transfers. Compliance certified.
I2C Master and Slave
Philips I2C standard implementation: 100 kbps normal, 400 kbps fast and 3.5 Mbps high-speed modes with multimaster operation.
Need a core customized — or one you don't see here?
Most of our IP is designed for easy customization, and we build cores to spec. Tell us your interface, process and performance targets.
Request a quote — info@asics.ws